There are several Three-Letter Acronyms (TLAs?) that start with the letters "DF"; Design for Manufacturability (DFM) includes Design for Test (DFT), Design for Assembly (DFA) and Design For Fabrication (DFF). There are a few others, such as Design for Reliability (DFR) or Design for Environment (DFE), and sometimes all of these together are referred to as DFx.
(DFx can also represent Design for Excellence, but either way, a DFX design is intended to please everyone!)

This section will be limited to DESIGN FOR MANUFACTURABILITY, so we will be looking at three major customers who are influenced by your design decisions

DESIGN FOR FAB

...to be continued...

DESIGN FOR ASSEMBLY

...to be continued...

DESIGN FOR TEST

The following checklist can be used when an In-Circuit Test (ICT) fixture will be developed for your design.

These guidelines do not address Flying Probe testers, Automated Optical Inspection (AOI), X-ray techniques or Boundary Scan

More information can be found in the Surface Mount Technology Association publication SMTA-TP-101 "Testability Guidelines", available HERE

SCHEMATIC CAPTURE

• Tie IC control lines high or low using individual pull-up or pull-down resistors
• Tie unused inputs high or low using individual pull-up or pull-down resistors
• Include method to disable clocks (can be accomplished using jumpers, tri-state buffer or enable line of oscillator if available)
• Provide disable methods for Programmable Logic Devices (PLDs), Application Specific Integrated Circuits (ASICs) and other custom devices
• Provide disable methods for Bussed Devices, High Current Devices, Flash RAMs, EEPROMS and D/A Converters
• Provide circuitry to disable digital feedback loops
• Provide a means to disable On-Board PROM
• Isolate Power-On Reset circuits from other digital circuits

CIRCUIT BOARD DESIGN

• Keep components and test points at least 3.2 mm (.125) from board edges (preferably 3.8 mm or .150 in)
• Provide at least two unplated 3.2 mm (0.125) diameter tooling holes, preferably in opposite corners, and leave 3.2 mm annular area around them free of components and test points. Consider using a "keying" pattern so boards can't be inserted backwards
• A double-sided test fixture is more expensive, so try to put all test points on one side of the board, usually the bottom or the side with the least circuit complexity. If top-side of board must be used for probe sites, use top only for non-critical nets. Keep test points for clocks, control pins, programming pins, serial data and boundary scan on bottom.
• Test point sites can be through-hole leads, dedicated pads or small diameter vias, but avoid placing test points on surface mount lands or gold-plated edge fingers. Don't use larger via diameters as test probe sites. Via hole size should be 0.36 mm (.014) or less
• For 100% testability, provide at least one test pad for each net
• Provide two pads on nets tied to critical low impedance devices (four-wire Kelvin testing)
• Provide 2-10 probe sites for primary power, and two test points each for isolated power/grounds. For primary ground provide many probe sites, one test point for every twenty grounds, or consider a grid of at least one per square inch
• Probe sites with 1.0 mm (.040) pad diameters are preferred, 0.9 mm (.035) is acceptable, 0.8 mm (.031) can be used if tooling holes are available for alignment, but smaller diameters will reduce contact repeatability
• Try to space probe sites at least 2.5 mm (.100) apart, center-to-center. In reality, 0.9 mm (.035) pads spaced 1.8 mm (.070) is considered standard by many. Closer spacing is possible but will require using thinner, less reliable and more expensive probes.
• Test points should be evenly distributed over the surface of the board. High stress in congested areas can cause board to warp.
• Keep tall components on the side that is not probed. The platen has to be cut out in places where components are over 6.4 mm (.255) tall on the probed side. For these, keep test points at least 5.0 mm (.200) away.
• For components taller than 2.6 mm (.100), maintain minimum 2.0 mm (.080) clearance edge-to-edge. For all other components, keep test pads at least 1.0 mm (.040) from component body, edge-to-edge.
• If Component Through-holes are used for test probe locations, make sure leads are robust enough for compressive force (be careful using LEDs or some types of transformers). Also, make sure PTH leads will be present on all versions of assembly (not depopulated)
• If design is panelized, try to include at least one tooling hole on each board in addition to the tooling holes in rails

Revising Designs with existing ICT Fixtures

It is often possible to modify an existing fixture to accommodate a revision instead of developing new one. This will be easier, faster and less expensive using the following guidelines:

• Do not move tooling pin holes.
• Do not move test points unless absolutely necessary.
• Do not put a new test point within 0.100" of an existing test point (or from a test point that is being removed).
• Do not rename existing components.
• Do not name new components with the same name as components that have been removed.
• If a connection on a net has changed, rename the net.
• If a net splits into two or more nets, don't re-use the old net name; create new net names.
• Keep the diameter of new test points at 0.040" to ensure a reliable contact. When fixture vendors re-drill holes for probe sockets into an existing fixture, they may not be as accurate as when the original fixture was fabricated.

(Thanks to Gary Ferrari and Deiter Bergman, my first "DFM Mentors")